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| 1999 microchip technology inc. ds40192c-page 1 device included in this data sheet: pic16c505 high-performance risc cpu: ? only 33 instructions to learn ? operating speed: - dc - 20 mhz clock input - dc - 200 ns instruction cycle ? direct, indirect and relative addressing modes for data and instructions ? 12-bit wide instructions ? 8-bit wide data path ? 2-level deep hardware stack ? eight special function hardware registers ? direct, indirect and relative addressing modes for data and instructions ? all single cycle instructions (200 ns) except for program branches which are two-cycle peripheral features: ? 11 i/o pins with individual direction control ? 1 input pin ? high current sink/source for direct led drive ? timer0: 8-bit timer/counter with 8-bit programmable prescaler pin diagram: device memory program data pic16c505 1024 x 12 72 x 8 pdip, soic, ceramic side brazed pic16c505 v dd rb5/osc1/clkin rb4/osc2/clkout rb3/mclr /v pp rc5/t0cki rc4 rc3 v ss rb0 rb1 rb2 rc0 rc1 rc2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 special microcontroller features: ? in-circuit serial programming (icsp?) ? power-on reset (por) ? device reset timer (drt) ? watchdog timer (wdt) with dedicated on-chip rc oscillator for reliable operation ? programmable code protection ? internal weak pull-ups on i/o pins ? wake-up from sleep on pin change ? power-saving sleep mode ? selectable oscillator options: - intrc: precision internal 4 mhz oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - hs: high speed crystal/resonator - lp: power saving, low frequency crystal cmos technology: ? low-power, high-speed cmos eprom technology ? fully static design ? wide operating voltage range (2.5v to 5.5v) ? wide temperature ranges - commercial: 0c to +70c - industrial: -40c to +85c - extended: -40c to +125c - < 1.0 m a typical standby current @ 5v ? low power consumption - < 2.0 ma @ 5v, 4 mhz -15 m a typical @ 3.0v, 32 khz for tmr0 running in sleep mode - < 1.0 m a typical standby current @ 5v pic16c505 14-pin, 8-bit cmos microcontroller
pic16c505 ds40192c-page 2 1999 microchip technology inc. table of contents 1.0 general description......................................................................................................... ............................................................ 3 2.0 pic16c505 device varieties .................................................................................................. ..................................................... 5 3.0 architectural overview ...................................................................................................... .......................................................... 7 4.0 memory organization ......................................................................................................... ....................................................... 11 5.0 i/o port .................................................................................................................... .................................................................. 19 6.0 timer0 module and tmr0 register ............................................................................................. ............................................. 23 7.0 special features of the cpu ................................................................................................. .................................................... 27 8.0 instruction set summary ..................................................................................................... ...................................................... 39 9.0 development support......................................................................................................... ....................................................... 51 10.0 electrical characteristics - pic16c505 ..................................................................................... ................................................ 57 11.0 dc and ac characteristics - pic16c505...................................................................................... ............................................ 71 11.0 packaging information...................................................................................................... ......................................................... 75 index .......................................................................................................................... .......................................................................... 79 on-line support................................................................................................................ ................................................................... 81 reader response ................................................................................................................ ................................................................ 82 pic16c505 product identification system ....................................................................................... ................................................... 83 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (480) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document. 1999 microchip technology inc. ds40192c-page 3 pic16c505 1.0 general description the pic16c505 from microchip technology is a low- cost, high-performance, 8-bit, fully static, eprom/ rom-based cmos microcontroller. it employs a risc architecture with only 33 single word/single cycle instructions. all instructions are single cycle (200 m s) except for program branches, which take two cycles. the pic16c505 delivers performance an order of mag- nitude higher than its competitors in the same price cat- egory. the 12-bit wide instructions are highly symmetrical resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. the easy to use and easy to remember instruction set reduces development time significantly. the pic16c505 product is equipped with special fea- tures that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are five oscillator configurations to choose from, including intrc internal oscillator mode and the power-saving lp (low power) oscillator mode. power saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the pic16c505 is available in the cost-effective one- time-programmable (otp) version, which is suitable for production in any volume. the customer can take full advantage of microchips price leadership in otp microcontrollers, while benefiting from the otps flexibility. the pic16c505 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a c compiler, a low-cost development pro- grammer and a full featured programmer. all the tools are supported on ibm pc and compatible machines. 1.1 applications the pic16c505 fits in applications ranging from per- sonal care appliances and security systems to low- power remote transmitters/receivers. the eprom technology makes customizing application programs (transmitter codes, appliance settings, receiver fre- quencies, etc.) extremely fast and convenient. the small footprint packages, for through hole or surface mounting, make this microcontroller perfect for applica- tions with space limitations. low-cost, low-power, high- performance, ease of use and i/o flexibility make the pic16c505 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of glue logic and plds in larger systems, and coprocessor applications). pic16c505 ds40192c-page 4 1999 microchip technology inc. table 1-1: pic16c505 device pic16c505 clock maximum frequency of operation (mhz) 20 memory eprom program memory 1024 data memory (bytes) 72 peripherals timer module(s) tmr0 wake-up from sleep on pin change yes features i/o pins 11 input pins 1 internal pull-ups yes in-circuit serial programming yes number of instructions 33 packages 14-pin dip, soic, jw the pic16c505 device has power-on reset, selectable watchdog timer, selectable code protect, high i/o current capability and precision internal oscillator. the pic16c505 device uses serial programming with data pin rb0 and clock pin rb1. 1999 microchip technology inc. ds40192c-page 5 pic16c505 2.0 pic16c505 device varieties a variety of packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic16c505 product identification system at the back of this data sheet to specify the correct part number. 2.1 uv erasable devices the uv erasable version, offered in a ceramic win- dowed package, is optimal for prototype development and pilot programs. the uv erasable version can be erased and reprogrammed to any of the configuration modes. microchip's picstart a plus and pro mate a ii pro- grammers all support programming of the pic16c505. third party programmers also are available; refer to the microchip third party guide, (ds00104), for a list of sources. 2.2 one-time-programmable (otp) devices the availability of otp devices is especially useful for customers who need the flexibility of frequent code updates or small volume applications. the otp devices, packaged in plastic packages, per- mit the user to program them once. in addition to the program memory, the configuration bits must also be programmed. note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be saved prior to erasing the part. 2.3 quick-turnaround-production (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program medium to high quantity units and whose code patterns have stabilized. the devices are identical to the otp devices but with all eprom locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please contact your local microchip technology sales office for more details. 2.4 serialized quick-turnaround production (sqtp sm ) devices microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry-code, password or id number. pic16c505 ds40192c-page 6 1999 microchip technology inc. notes: 1999 microchip technology inc. ds40192c-page 7 pic16c505 3.0 architectural overview the high performance of the pic16c505 can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16c505 uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide, making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (200ns @ 20mhz) except for program branches. the table below lists program memory (eprom) and data memory (ram) for the pic16c505. the pic16c505 can directly or indirectly address its register files and data memory. all special function registers, including the program counter, are mapped in the data memory. the pic16c505 has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of special optimal situations make programming with the pic16c505 simple yet efficient. in addition, the learning curve is reduced significantly. device memory program data pic16c505 1024 x 12 72 x 8 the pic16c505 device contains an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, one operand is typically the w (working) register. the other operand is either a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1. pic16c505 ds40192c-page 8 1999 microchip technology inc. figure 3-1: pic16c505 block diagram device reset timer power-on reset watchdog timer eprom program memory 12 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation osc1/clkin osc2 mclr v dd , v ss timer0 portb 8 8 rb4/osc2/clkout rb3/mclr /v pp rb2 rb1 rb0 5-7 3 rb5/osc1/clkin stack1 stack2 1k x 12 7 2 b y t e s internal rc osc portc rc4 rc3 rc2 rc1 rc0 rc5/t0cki 1999 microchip technology inc. ds40192c-page 9 pic16c505 table 3-1: pic16c505 pinout description name dip pin # soic pin # i/o/p type buffer type description rb0 13 13 i/o ttl/st bi-directional i/o port/ serial programming data. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. this buffer is a schmitt trigger input when used in serial programming mode. rb1 12 12 i/o ttl/st bi-directional i/o port/ serial programming clock. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. this buffer is a schmitt trigger input when used in serial programming mode. rb2 11 11 i/o ttl bi-directional i/o port. rb3/mclr /v pp 4 4 i ttl/st input port/master clear (reset) input/programming volt- age input. when configured as mclr , this pin is an active low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. weak pull- up only when configured as rb3. st when configured as mclr . rb4/osc2/clkout 3 3 i/o ttl bi-directional i/o port/oscillator crystal output. con- nections to crystal or resonator in crystal oscillator mode (xt and lp modes only, rb4 in other modes). can be software programmed for internal weak pull-up and wake-up from sleep on pin change. in extrc and intrc modes, the pin output can be configured to clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. rb5/osc1/clkin 2 2 i/o ttl/st bidirectional io port/oscillator crystal input/external clock source input (rb5 in internal rc mode only, osc1 in all other oscillator modes). ttl input when rb5, st input in external rc oscillator mode. rc0 10 10 i/o ttl bi-directional i/o port. rc1 9 9 i/o ttl bi-directional i/o port. rc2 8 8 i/o ttl bi-directional i/o port. rc3 7 7 i/o ttl bi-directional i/o port. rc4 6 6 i/o ttl bi-directional i/o port. rc5/t0cki 5 5 i/o st bi-directional i/o port. can be configured as t0cki. v dd 11p positive supply for logic and i/o pins v ss 14 14 p ground reference for logic and i/o pins legend: i = input, o = output, i/o = input/output, p = power, = not used, ttl = ttl input, st = schmitt trigger input pic16c505 ds40192c-page 10 1999 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter is incremented every q1, and the instruction is fetched from program memory and latched into the instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is flushed from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf portb, bit1 fetch 4 flush fetch sub_1 execute sub_1 1999 microchip technology inc. ds40192c-page 11 pic16c505 4.0 memory organization pic16c505 memory is organized into program mem- ory and data memory. for the pic16c505, a paging scheme is used. program memory pages are accessed using one status register bit. data mem- ory banks are accessed using the file select register (fsr). 4.1 program memory organization the pic16c505 devices have a 12-bit program counter (pc). the 1k x 12 (0000h-03ffh) for the pic16c505 are physically implemented. refer to figure 4-1. accessing a location above this boundary will cause a wrap-around within the first 1k x 12 space. the effective reset vector is at 0000h, (see figure 4-1). location 03ffh contains the internal clock oscillator calibration value. this value should never be overwritten. figure 4-1: program memory map and stack for the pic16c505 call, retlw pc<11:0> stack level 1 stack level 2 user memory space 12 0000h 7ffh 01ffh 0200h reset vector (note 1) note 1: address 0000h becomes the effective reset vector. location 03ffh contains the movlw xx internal rc oscillator calibration value. 1024 words 03ffh 0400h on-chip program memory pic16c505 ds40192c-page 12 1999 microchip technology inc. 4.2 data memory organization data memory is composed of registers or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers and general purpose registers. the special function registers include the tmr0 register, the program counter (pcl), the status register, the i/o registers (ports) and the file select register (fsr). in addition, special function registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic16c505, the register file is composed of 8 special function registers, 24 general purpose registers and 48 general purpose registers that may be addressed using a banking scheme (figure 4-2). 4.2.1 general purpose register file the general purpose register file is accessed, either directly or indirectly, through the file select register fsr (section 4.8). figure 4-2: pic16c505 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal portb 0fh 10h bank 0 bank 1 3fh 30h 20h 2fh general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. fsr<6:5> 00 01 bank 3 7fh 70h 60h 6fh general purpose registers 11 bank 2 5fh 50h 40h 4fh general purpose registers 10 08h portc 1999 microchip technology inc. ds40192c-page 13 pic16c505 4.2.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special function registers can be classified into two sets. the special function registers associated with the core functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function register (sfr) summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets (2) 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h (1) pcl low order 8 bits of pc 1111 1111 1111 1111 03h status rbwuf paoto pd zdcc 0001 1xxx q00q quuu (1) 04h fsr indirect data memory address pointer 110x xxxx 11uu uuuu 05h osccal cal5 cal4 cal3 cal2 cal1 cal0 1000 00-- uuuu uu-- n/a trisb i/o control registers --11 1111 --11 1111 n/a trisc i/o control registers --11 1111 --11 1111 n/a option rbwu rbpu tocs tose psa ps2 ps1 ps0 1111 1111 1111 1111 06h portb rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu 07h portc rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu legend: shaded cells not used by port registers, read as 0, = unimplemented, read as 0, x = unknown, u = unchanged, q = depends on condition. note 1: if reset was due to wake-up on pin change, then bit 7 = 1. all other rests will cause bit 7 = 0. note 2: other (non-power-up) resets include external reset through mclr , watchdog timer and wake-up on pin change reset. pic16c505 ds40192c-page 14 1999 microchip technology inc. 4.3 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bit. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status register, because these instructions do not affect the z, dc or c bits from the status register. for other instructions, which do affect status bits, see instruction set summary. register 4-1: status register (address:03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x rbwuf pa 0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7: rbwuf : i/o reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power up or other reset bit 6: unimplemented bit 5: pa0 : program page preselect bits 1 = page 1 (200h - 3ffh) 0 = page 0 (000h - 1ffh) each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred 1999 microchip technology inc. ds40192c-page 15 pic16c505 4.4 option register the option register is a 8-bit wide, write-only register, which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option<7:0> bits. note: if tris bit is set to 0, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that tris overrides option control of rbpu and rbwu) . register 4-2: option register w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 rbwu rbpu t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7: rbwu : enable wake-up on pin change (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 6: rbpu : enable weak pull-ups (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin (overrides tris pic16c505 ds40192c-page 16 1999 microchip technology inc. 4.5 osccal register the oscillator calibration (osccal) register is used to calibrate the internal 4 mhz oscillator. it contains six bits for calibration after you move in the calibration constant, do not change the value. see section 7.2.5 note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part, so it can be repro- grammed correctly later. register 4-3: osccal register (address 05h) pic16c505 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 cal5 cal4 cal3 cal2 cal1 cal0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-2: cal<5:0>: calibration bit 1-0: unimplemented read as 0 1999 microchip technology inc. ds40192c-page 17 pic16c505 4.6 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0>. bit 5 of the status register provides page information to bit 9 of the pc (figure 4-3). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-3). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc, and bsf pc,5. figure 4-3: loading of pc branch instructions - pic16c505 note: because pc<8> is cleared in the call instruction or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). pa 0 status pc 87 0 pcl 9 10 instruction word 70 goto instruction call or modify pcl instruction 11 pa 0 status pc 87 0 pcl 9 10 instruction word 70 11 reset to 0 4.6.1 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the oscillator calibration instruction.) after executing movlw xx , the pc will roll over to location 00h and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre- selected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.7 stack pic16c505 devices have a 12-bit wide hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in level 2. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory. note 1: there are no status bits to indicate stack overflows or stack underflow condi- tions. note 2: there are no instructions mnemonics called push or pop . these are actions that occur from the execution of the call, retlw , and instructions. pic16c505 ds40192c-page 18 1999 microchip technology inc. 4.8 indirect data addressing; indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-1: indirect addressing ? register file 07 contains the value 10h ? register file 08 contains the value 0ah ? load the value 07 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 08) ? a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-2. example 4-2: how to clear ram using indirect addressing movlw 0x10 ;initialize pointer movwf fsr ; to ram next clrf indf ;cl ear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue : the fsr is a 5-bit wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. the device uses fsr<6:5> to select between banks 0:3. figure 4-4: direct/indirect addressing note 1: for register map detail see section 4.2. direct addressing (fsr) 6 5 4 (opcode) 0 bank select location select 00 01 10 11 00h 0fh 10h data memory (1) 1fh 3fh 5fh 7fh bank 0 bank 1 bank 2 bank 3 addresses map back to addresses in bank 0. indirect addressing 6 5 4 (fsr) 0 bank location select 1999 microchip technology inc. ds40192c-page 19 pic16c505 5.0 i/o port as with any other register, the i/o register can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pins input/output modes. on reset, all i/o ports are defined as input (inputs are at hi-impedance) since the i/o control registers are all set. 5.1 portb portb is an 8-bit i/o register. only the low order 6 bits are used (rb<5:0>). bits 7 and 6 are unimplemented and read as '0's. please note that rb3 is an input only pin. the configuration word can set several i/os to alternate functions. when acting as alternate functions, the pins will read as 0 during port read. pins rb0, rb1, rb3 and rb4 can be configured with weak pull-ups and also with wake-up on change. the wake-up on change and weak pull-up functions are not pin selectable. if pin 4 is configured as mclr , weak pull-up is always off and wake-up on change for this pin is not enabled. 5.2 portc portc is an 8-bit i/o register. only the low order 6 bits are used (rc<5:0>). bits 7 and 6 are unimplemented and read as 0s. 5.3 tris registers the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the exceptions are rb3, which is input only, and rc5, which may be controlled by the option register. see register 4-2. the tris registers are write-only and are set (output drivers disabled) upon reset. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 5.4 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1. all port pins except rb3, which is input only, may be used for both input and output operations. for input operations, these ports are non-latching. any input must be present until read by an input instruction (e.g., movf portb,w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit in tris must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin (except rb3) can be programmed individually as input or output. figure 5-1: equivalent circuit for a single i/o pin data bus q d q ck q d q ck p n wr port tris f data tris rd port v ss v dd i/o pin (1) w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . note 2: see table 3-1 for buffer type. (2) pic16c505 ds40192c-page 20 1999 microchip technology inc. table 5-1: summary of port registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a trisb i/o control registers --11 1111 --11 1111 n/a trisc i/o control registers --11 1111 --11 1111 n/a option rbwu rbpu tocs tose psa ps2 ps1 ps0 1111 1111 1111 1111 03h status rbwuf pao to pd z dc c 0001 1xxx q00q quuu (1) 06h portb rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu 07h portc rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu legend: shaded cells not used by port registers, read as 0, = unimplemented, read as 0, x = unknown, u = unchanged, q = depends on condition. note 1: if reset was due to wake-up on pin change, then bit 7 = 1. all other rests will cause bit 7 = 0. 5.5 i/o programming considerations 5.5.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu, bit5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bi- directional i/o pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wired- and). the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port ;initial portb settings ; portb<5:3> inputs ; portb<2:0> outputs ; ; portb latch portb pins ; ---------- ---------- bcf portb, 5 ;--01 -ppp --11 pppp bcf portb, 4 ;--10 -ppp --11 pppp movlw 007h ; tris portb ;--10 -ppp --11 pppp ; ;note that the user may have expected the pin ;values to be --00 pppp. the 2nd bcf caused ;rb5 to be latched as the pin value (high). 5.5.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. 1999 microchip technology inc. ds40192c-page 21 pic16c505 figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<5:0> movwf portb nop port pin sampled here nop movf portb,w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. data setup time = (0.25 t cy C t pd ) where: t cy = instruction cycle. t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read portb) por t pin written here pic16c505 ds40192c-page 22 1999 microchip technology inc. notes: 1999 microchip technology inc. ds40192c-page 23 pic16c505 6.0 timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 - readable and writable ? 8-bit software programmable prescaler ? internal or external clock select - edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit (option<4>) determines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1. the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-5). 0 1 1 0 t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 t cy delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync t0se rc5/t0cki pin pic16c505 ds40192c-page 24 1999 microchip technology inc. figure 6-2: timer0 timing: internal clock/no prescale figure 6-3: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a trisc rc5 rc4 rc3 rc2 rc1 rc0 --11 1111 --11 1111 legend: shaded cells not used by timer0, - = unimplemented, x = unknown, u = unchanged. pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0 1999 microchip technology inc. ds40192c-page 25 pic16c505 6.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-4). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-4 shows the delay from the external clock edge to the timer incrementing. figure 6-4: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2: 3: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. external clock if no prescaler selected; prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1) pic16c505 ds40192c-page 26 1999 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (section 7.6). for simplicity, this counter is being referred to as prescaler throughout this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all '0's. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed on-the-fly during program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 ? wdt) 1.clrwdt ;clear wdt 2.clrf tmr0 ;clear tmr0 & prescaler 3.movlw '00xx1111b ;these 3 lines (5, 6, 7) 4.option ; are required only if ; desired 5.clrwdt ;ps<2:0> are 000 or 001 6.movlw '00xx1xxxb ;set postscaler to 7.option ; desired wdt rate to change prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler movlw 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option figure 6-5: block diagram of the timer0/wdt prescaler t cy ( = fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 note: t0cs, t0se, psa, ps<2:0> are bits in the option register. psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x t0se rc5/t0cki pin 1999 microchip technology inc. ds40192c-page 27 pic16c505 7.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. the pic16c505 microcontroller has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these features are: ? oscillator selection ? reset - power-on reset (por) - device reset timer (drt) - wake-up from sleep on pin change ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming ?clock out the pic16c505 has a watchdog timer, which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. if using hs, xt or lp selectable oscillator options, there is always an 18 ms (nominal) delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. if using intrc or extrc, there is an 18 ms delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through a change on input pins or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application, including an internal 4 mhz oscillator. the extrc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 7.1 configuration bits the pic16c505 configuration word consists of 12 bits. configuration bits can be programmed to select various device configurations. three bits are for the selection of the oscillator type, one bit is the watchdog timer enable bit, and one bit is the mclr enable bit. seven bits are for code protection (register 7-1). register 7-1: configuration word for pic16c505 cp cp cp cp cp cp mclre cp wdte fosc2 fosc1 fosc0 register: config address (2) : 0fffh bit1110987654321 bit0 bit 11-6, 4: cp code protection bits (1)(2)(3) bit 5: mclre: rb3/mclr pin function select 1 = rb3/mclr pin function is mclr 0 = rb3/mclr pin function is digital i/o, mclr internally tied to v dd bit 3: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0: fosc<1:0>: oscillator selection bits 111 = external rc oscillator/clkout function on rb4/osc2/clkout pin 110 = external rc oscillator/rb4 function on rb4/osc2/clkout pin 101 = internal rc oscillator/clkout function on rb4/osc2/clkout pin 100 = internal rc oscillator/rb4 function on rb4/osc2/clkout pin 011 = invalid selection 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator note 1: 03ffh is always uncode protected on the pic16c505. this location contains the movlwxx calibration instruction for the intrc. 2: refer to the pic16c505 programming specifications to determine how to access the con- figuration word. this register is not user addressable during device operation. 3: all code protect bits must be written to the same value. pic16c505 ds40192c-page 28 1999 microchip technology inc. 7.2 oscillator configurations 7.2.1 oscillator types the pic16c505 can be operated in four different oscillator modes. the user can program three configuration bits (fosc<2:0>) to select one of these four modes: ? lp: low power crystal ? xt: crystal/resonator ? hs: high speed crystal/resonator ? intrc: internal 4 mhz oscillator ? extrc: external resistor/capacitor 7.2.2 crystal oscillator / ceramic resonators in hs, xt or lp modes, a crystal or ceramic resonator is connected to the rb5/osc1/clkin and rb4/ osc2/clkout pins to establish oscillation (figure 7-1). the pic16c505 oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in hs, xt or lp modes, the device can have an external clock source drive the rb5/osc1/clkin pin (figure 7-2). figure 7-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 7-2: external clock input operation (hs, xt or lp osc configuration) note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf approx. value = 10 m w . c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic16c505 clock from ext. system osc1 osc2 pic16c505 open table 7-1: capacitor selection for ceramic resonators - pic16c505 table 7-2: capacitor selection for crystal oscillator - pic16c505 osc type resonator freq cap. range c1 cap. range c2 xt 4.0 mhz 30 pf 30 pf hs 16 mhz 10-47 pf 10-47 pf these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf hs 20 mhz 15-47 pf 15-47 pf note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. these values are for design guidance only. rs may be required to avoid overdriving crystals with low drive level specification. since each crystal has its own characteristics, the user should consult the crys- tal manufacturer for appropriate values of external components. 1999 microchip technology inc. ds40192c-page 29 pic16c505 7.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 7-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 7-3: external parallel resonant crystal oscillator circuit figure 7-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 w resistors provide the negative feedback to bias the inverters in their linear region. figure 7-4: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c505 clkin to other devices 330 74as04 74as04 pic16c505 clkin to o t h e r devices xtal 330 74as04 0.1 mf 7.2.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 7-5 shows how the r/c combination is connected to the pic16c505. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g., 1 m w ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. the electrical specifications section shows rc frequency variation from part to part due to normal process variation. the variation is larger for larger values of r (since leakage current variation will affect rc frequency more for large r) and for smaller values of c (since variation of input capacitance will affect rc frequency more). also, see the electrical specifications section for variation of oscillator frequency due to v dd for given rext/cext values, as well as frequency variation due to operating temperature for given r, c and v dd values. figure 7-5: external rc oscillator mode v dd rext cext v ss osc1 internal clock pic16c505 n f osc /4 osc2/clkout pic16c505 ds40192c-page 30 1999 microchip technology inc. 7.2.5 internal 4 mhz rc oscillator the internal rc oscillator provides a fixed 4 mhz (nom- inal) system clock at v dd = 5v and 25c, see electrical specifications section for information on variation over voltage and temperature. in addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal rc oscillator. this location is always protected, regardless of the code protect set- tings. this value is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. osccal, when written to with the calibration value, will trim the internal oscillator to remove process variation from the oscillator frequency. for the pic16c505, only bits <7:2> of osccal are implemented. 7.3 reset the device differentiates between various kinds of reset: a) power on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt time-out reset during normal operation e) wdt time-out reset during sleep f) wake-up from sleep on pin change some registers are not reset in any way, they are unknown on por and unchanged in any other reset. most other registers are reset to reset state on power- on reset (por), mclr , wdt or wake-up on pin change reset during normal operation. they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal operation. the exceptions to this are to , pd and rbwuf bits. they are set or cleared differently in different reset situations. these bits are used in software to determine the nature of reset. see table 7-3 for a full description of reset states of all registers. note: please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be repro- grammed correctly later. 1999 microchip technology inc. ds40192c-page 31 pic16c505 table 7-3: reset conditions for registers table 7-4: reset condition for special registers register address power-on reset mclr reset wdt time-out wake-up on pin change w qqqq qqqq (1) qqqq qqqq (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0001 1xxx q00q quuu (2,3) fsr 04h 110x xxxx 11uu uuuu osccal 05h 1000 00-- uuuu uu-- portb 06h --xx xxxxx --uu uuuu portc 07h --xx xxxxx --uu uuuu option 1111 1111 1111 1111 trisb --11 1111 --11 1111 trisc --11 1111 --11 1111 legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition. note 1: bits <7:2> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. note 2: see table 7-7 for reset value for specific conditions. note 3: if reset was due to wake-up on pin change, then bit 7 = 1. all other resets will cause bit 7 = 0. status addr: 03h pcl addr: 02h power on reset 0001 1xxx 1111 1111 mclr reset during normal operation 000u uuuu 1111 1111 mclr reset during sleep 0001 0uuu 1111 1111 wdt reset during sleep 0000 0uuu 1111 1111 wdt reset normal operation 0000 uuuu 1111 1111 wake-up from sleep on pin change 1001 0uuu 1111 1111 legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0. pic16c505 ds40192c-page 32 1999 microchip technology inc. 7.3.1 mclr enable this configuration bit when unprogrammed (left in the 1 state) enables the external mclr function. when programmed, the mclr function is tied to the internal v dd , and the pin is assigned to be a i/o. see figure 7-6. figure 7-6: mclr select 7.4 power-on reset (por) the pic16c505 family incorporates on-chip power-on reset (por) circuitry, which provides an internal chip reset for most power-up situations. the on chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. to take advantage of the internal por, program the rb3/mclr /v pp pin as mclr and tie through a resistor to v dd or program the pin as rb3. an internal weak pull-up resistor is implemented using a transistor. refer to table 10-1 for the pull-up resistor ranges. this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified. see electrical specifications for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 7-7. rb3/mclr /v pp mclre internal mclr weak pull-up rbwu the power-on reset circuit and the device reset timer (section 7.5) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- chip reset signal. a power-up example where mclr is held low is shown in figure 7-8. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-9, the on-chip power-on reset feature is being used (mclr and v dd are tied together or the pin is programmed to be rb3.). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 7-10 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when mclr and v dd actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip may not function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 7-9). for additional information refer to application notes power-up considerations - an522 and power-up trouble shooting - an607. note: when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, tempera- ture, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. 1999 microchip technology inc. ds40192c-page 33 pic16c505 figure 7-7: simplified block diagram of on-chip reset circuit figure 7-8: time-out sequence on power-up (mclr pulled low) figure 7-9: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd rb3/mclr /v pp power-up detect on-chip drt osc por (power-on reset) wdt time-out reset chip reset 8-bit asynch ripple counter (start-up timer) mclre sleep pin change wake-up on pin change v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt pic16c505 ds40192c-page 34 1999 microchip technology inc. figure 7-10: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset t drt v1 note: when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 3 v dd min. 7.5 device reset timer (drt) in the pic16c505, the drt runs any time the device is powered up. drt runs from reset and varies based on oscillator selection and reset type (see table 7-5). the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min. and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition for approximately 18 ms after mclr has reached a logic high (v ih mclr ) level. thus, programming rb3/mclr /v pp as mclr and using an external rc network connected to the mclr input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the rb3/ mclr /v pp pin as a general purpose input. the device reset time delay will vary from chip to chip due to v dd , temperature and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out. this is particularly important for applications using the wdt to wake from sleep mode automatically. reset sources are por, mclr , wdt time-out and wake-up on pin change. (see section 7.9.2, notes 1, 2, and 3, page 37.) 7.6 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator, which does not require any external components. this rc oscillator is separate from the external rc oscillator of the rb5/osc1/clkin pin and the internal 4 mhz oscillator. that means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the to bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by programming the configuration bit wdte as a '0' (section 7.1). refer to the pic16c505 programming specifications to determine how to access the configuration word. table 7-5: drt (device reset timer period) oscillator configuration por reset subsequent resets intrc & extrc 18 ms (typical) 300 s (typical) hs, xt & lp 18 ms (typical) 18 ms (typical) 1999 microchip technology inc. ds40192c-page 35 pic16c505 7.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to- part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 7.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. figure 7-11: watchdog timer block diagram table 7-6: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a option rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer, = unimplemented, read as '0', u = unchanged. 1 0 1 0 from timer0 clock source (figure 6-5) to timer0 (figure 6-4) postscaler wdt enable configuration bit psa wdt time-out ps<2:0> psa mux 8 - to - 1 mux postscaler m u x watchdog timer note: t0cs, t0se, psa, ps<2:0> are bits in the option register. pic16c505 ds40192c-page 36 1999 microchip technology inc. 7.7 time-out sequence, power down, and wake-up from sleep status bits ( to / pd /rbwuf) the to , pd , and rbwuf bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset. 7.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic16c505 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 7-12 and figure 7-13. figure 7-12: brown-out protection circuit 1 table 7-7: to /pd /rbwuf status after reset rbwuf to pd reset caused by 000 wdt wake-up from sleep 00u wdt time-out (not from sleep) 010 mclr wake-up from sleep 011 power-up 0uu mclr not during sleep 110 wake-up from sleep on pin change legend: u = unchanged note 1: the to , pd , and rbwuf bits maintain their status (u) until a reset occurs. a low-pulse on the mclr input does not change the to , pd , and rbwuf status bits. this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). note 1: pin must be confirmed as mclr . 33k 10k 40k* v dd mclr (1) pic16c505 v dd q1 figure 7-13: brown-out protection circuit 2 figure 7-14: brown-out protection circuit 3 this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: note 1: pin must be confirmed as mclr . v dd ? r1 r1 + r2 = 0.7v r2 40k* v dd mclr (1) pic16c505 r1 q1 v dd this brown-out protection circuit employs microchip technologys mcp809 microcontroller supervisor. there are 7 different trip point selections to accommodate 5v to 3v systems. mclr pic12c5xx v dd v dd v ss rst mcp809 v dd bypass capacitor 1999 microchip technology inc. ds40192c-page 37 pic16c505 7.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 7.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the mclr pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the rb3/ mclr /v pp pin must be at a logic high level (v ihmc ) if mclr is enabled. 7.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on rb3/mclr /v pp pin, when configured as mclr . 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pin rb0, rb1, rb3 or rb4 when wake-up on change is enabled. these events cause a device reset. the to , pd , and rbwuf bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the rbwuf bit indicates a change in state while in sleep at pins rb0, rb1, rb3 or rb4 (since the last file or bit operation on rb port). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. caution: right before entering sleep, read the input pins. when in sleep, wake up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before reentering sleep, a wake-up will occur immediately even if no pins change while in sleep mode. 7.10 program verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations and the last location (osccal) can be read, regardless of the code protection bit setting. 7.11 id locations four memory locations are designated as id locations where the user can store checksum or other code- identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as '0's. pic16c505 ds40192c-page 38 1999 microchip technology inc. 7.12 in-circuit serial programming the pic16c505 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. the device is placed into a program/verify mode by holding the rb1 and rb0 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). rb1 becomes the programming clock and rb0 becomes the programming data. both rb1 and rb0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c505 programming specifications. a typical in-circuit serial programming connection is shown in figure 7-15. figure 7-15: typical in-circuit serial programming connection external connector signals to n o r m a l connections to n o r m a l connections pic16c505 v dd v ss mclr /v pp rb1 rb0 +5v 0v v pp clk data i/o v dd 1999 microchip technology inc. ds40192c-page 39 pic16c505 8.0 instruction set summary each pic16c505 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the pic16c505 instruction set summary in table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. table 8-1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. the file register designator is used to specify which one of the 32 file registers is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is '0', the result is placed in the w register. if 'd' is '1', the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. table 8-1: opcode field descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register 'f') default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents ? assigned to < > register bit field ? in the set of i talics user defined term (font is courier) all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 m s. figure 8-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where 'h' signifies a hexadecimal digit. figure 8-1: general format for instructions byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value pic16c505 ds40192c-page 40 1999 microchip technology inc. table 8-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f C f, d f, d f, d f, d f, d f, d f, d f C f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k C k C f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a '0' by any instruction that writes to the pc except for goto . (section 4.6) 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: the instruction tris f , where f = 6 causes the contents of the w register to be written to the tristate latches of portb. a '1' forces the pin to a hi-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0). 1999 microchip technology inc. ds40192c-page 41 pic16c505 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d ? [0,1] operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is '1', the result is stored back in reg- ister 'f'. words: 1 cycles: 1 example: addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) ? (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are anded with the eight-bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: andlw 0x5f before instruction w= 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d ? [0,1] operation: (w) .and. (f) ? (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are anded with register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is '1', the result is stored back in register 'f'. words: 1 cycles: 1 example: andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 ? (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 pic16c505 ds40192c-page 42 1999 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 ? (f) status affected: none encoding: 0101 bbbf ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit 'b' in register 'f' is 0, then the next instruction is skipped. if bit 'b' is 0, then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code before instruction pc = address (here) after instruction if flag<1>=0, pc = address (true) ; if flag<1>=1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit 'b' in register 'f' is '1', then the next instruction is skipped. if bit 'b' is '1', then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1>=1, pc = address (true) 1999 microchip technology inc. ds40192c-page 43 pic16c505 call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 ? top of stack; k ? pc<7:0>; (status<6:5>) ? pc<10:9>; 0 ? pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h ? (f); 1 ? z status affected: z encoding: 0000 011f ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w); 1 ? z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt; 0 ? wdt prescaler (if assigned); 1 ? to; 1 ? pd status affected: to , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescale = 0 to =1 pd =1 pic16c505 ds40192c-page 44 1999 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 0010 01df ffff description: the contents of register 'f' are complemented. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in regis- ter 'f'. words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w=0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d ? [0,1] operation: (f) C 1 ? (dest) status affected: z encoding: 0000 11df ffff description: decrement register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d ? [0,1] operation: (f) C 1 ? d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register 'f' are dec- remented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 0, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt 1 0, pc = address (here+1) goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k ? pc<8:0>; status<6:5> ? pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there) 1999 microchip technology inc. ds40192c-page 45 pic16c505 incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 0010 10df ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. if the result is 0, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two cycle instruction. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt 1 0, pc = address (here +1) pic16c505 ds40192c-page 46 1999 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) ? (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are ored with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: iorlw 0x35 before instruction w = 0x9a after instruction w= 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d ? [0,1] operation: (w).or. (f) ? (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with register 'f'. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0 movf move f syntax: [ label ] movf f,d operands: 0 f 31 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 0010 00df ffff description: the contents of register 'f' are moved to destination 'd'. if 'd' is 0, destination is the w register. if 'd' is 1, the destination is file register 'f'. 'd' = 1 is useful as a test of a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal 'k' is loaded into the w register. the dont cares will assembled as 0s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a 1999 microchip technology inc. ds40192c-page 47 pic16c505 movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) ? (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to register 'f'. words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example option before instruction w = 0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ;w now has table ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 pic16c505 ds40192c-page 48 1999 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is stored back in regis- ter 'f'. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 c register 'f' rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0, the result is placed in the w register. if 'd' is 1, the result is placed back in reg- ister 'f'. words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 c register 'f' 1999 microchip technology inc. ds40192c-page 49 pic16c505 sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt prescaler; 1 ? to ; 0 ? pd status affected: to , pd, rbwuf encoding: 0000 0000 0011 description: time-out status bit (to ) is set. the power down status bit (pd ) is cleared. rbwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section on sleep for more details. words: 1 cycles: 1 example: sleep subwf subtract w from f syntax: [ label ]subwf f,d operands: 0 f 31 d ? [0,1] operation: (f) C (w) ? ( dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2s complement method) the w register from register 'f'. if 'd' is 0, the result is stored in the w register. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive example 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero example 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = ff w=2 c = 0 ; result is negative pic16c505 ds40192c-page 50 1999 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>); (f<7:4>) ? (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0, the result is placed in w regis- ter. if 'd' is 1, the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) ? tris register f status affected: none encoding: 0000 0000 0fff description: tris register 'f' (f = 6 or 7) is loaded with the contents of the w register words: 1 cycles: 1 example tris portb before instruction w=0xa5 after instruction tris = 0xa5 xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xored with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: xorlw 0xaf before instruction w= 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d ? [0,1] operation: (w) .xor. (f) ? ( dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0, the result is stored in the w regis- ter. if 'd' is 1, the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5 ? 1999 microchip technology inc. ds40192c-page 51 pic16c505 9.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab? ide software ? assemblers/compilers/linkers - mpasm assembler - mplab-c17 and mplab-c18 c compilers - mplink/mplib linker/librarian ? simulators - mplab-sim software simulator ?emulators - mplab-ice real-time in-circuit emulator - picmaster ? /picmaster-ce in-circuit emulator - icepic? ? in-circuit debugger - mplab-icd for pic16f877 ? device programmers -pro mate a ii universal programmer - picstart a plus entry-level prototype programmer ? low-cost demonstration boards - simice - picdem-1 - picdem-2 - picdem-3 - picdem-17 - seeval a -k ee l oq a 9.1 mplab integrated development environment software ? the mplab ide software brings an ease of soft- ware development previously unseen in the 8-bit microcontroller market. mplab is a windows a - based application which contains: ? multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) ? a full featured editor ? a project manager ? customizable tool bar and key mapping ? a status bar ? on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) ? debug using: - source files - absolute listing file - object code the ability to use mplab with microchips simulator, mplab-sim, allows a consistent platform and the abil- ity to easily switch from the cost-effective simulator to the full featured emulator with minimal retraining. 9.2 mpasm assembler mpasm is a full featured universal macro assembler for all picmicro mcus. it can produce absolute code directly in the form of hex files for device program- mers, or it can generate relocatable objects for mplink. mpasm has a command line interface and a windows shell and can be used as a standalone application on a windows 3.x or greater system. mpasm generates relocatable object files, intel standard hex files, map files to detail memory usage and symbol reference, an absolute lst file which contains source lines and gen- erated machine code, and a cod file for mplab debugging. mpasm features include: ? mpasm and mplink are integrated into mplab projects. ? mpasm allows user defined macros to be created for streamlined assembly. ? mpasm allows conditional assembly for multi pur- pose source files. ? mpasm directives allow complete control over the assembly process. 9.3 mplab-c17 and mplab-c18 c compilers the mplab-c17 and mplab-c18 code development systems are complete ansi c compilers and inte- grated development environments for microchips pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display. pic16c505 ds40192c-page 52 ? 1999 microchip technology inc. 9.4 mplink/mplib linker/librarian mplink is a relocatable linker for mpasm and mplab-c17 and mplab-c18. it can link relocatable objects from assembly or c source files along with pre- compiled libraries using directives from a linker script. mplib is a librarian for pre-compiled code to be used with mplink. when a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application. this allows large libraries to be used efficiently in many dif- ferent applications. mplib manages the creation and modification of library files. mplink features include: ? mplink works with mpasm and mplab-c17 and mplab-c18. ? mplink allows all memory areas to be defined as sections to provide link-time flexibility. mplib features include: ? mplib makes linking easier because single librar- ies can be included instead of many smaller files. ? mplib helps keep code maintainable by grouping related modules together. ? mplib commands allow libraries to be created and modules to be added, listed, replaced, deleted, or extracted. 9.5 mplab-sim software simulator the mplab-sim software simulator allows code development in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file or user-defined key press to any of the pins. the execution can be performed in single step, execute until break, or trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mplab-c18 and mpasm. the soft- ware simulator offers the flexibility to develop and debug code outside of the laboratory environment mak- ing it an excellent multi-project software development tool. 9.6 mplab-ice high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of mplab-ice is provided by the mplab integrated development environment (ide), which allows editing, make and download, and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support new picmicro microcon- trollers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc platform and microsoft ? windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. mplab-ice 2000 is a full-featured emulator system with enhanced trace, trigger, and data monitoring fea- tures. both systems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 9.7 picmaster/picmaster ce the picmaster system from microchip technology is a full-featured, professional quality emulator system. this flexible in-circuit emulator provides a high-quality, universal platform for emulating microchip 8-bit picmicro microcontrollers (mcus). picmaster sys- tems are sold worldwide, with a ce compliant model available for european union (eu) countries. 9.8 icepic icepic is a low-cost in-circuit emulation solution for the microchip technology pic16c5x, pic16c6x, pic16c7x, and pic16cxxx families of 8-bit one-time- programmable (otp) microcontrollers. the modular system can support different subsets of pic16c5x or pic16cxxx products through the use of interchangeable personality modules or daughter boards. the emulator is capable of emulating without target application circuitry being present. 9.9 mplab-icd in-circuit debugger microchip's in-circuit debugger, mplab-icd, is a pow- erful, low-cost run-time development tool. this tool is based on the flash pic16f877 and can be used to develop for this and other picmicro microcontrollers from the pic16cxxx family. mplab-icd utilizes the in-circuit debugging capability built into the pic16f87x. this feature, along with microchip's in-cir- cuit serial programming protocol, offers cost-effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. the mplab-icd is also a programmer for the flash pic16f87x family. ? 1999 microchip technology inc. ds40192c-page 53 pic16c505 9.10 pro mate ii universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode the pro mate ii can read, verify or program picmicro devices. it can also set code-protect bits in this mode. 9.11 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus supports all picmicro devices with up to 40 pins. larger pin count devices such as the pic16c92x, and pic17c76x may be supported with an adapter socket. picstart plus is ce compliant. 9.12 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab-sim. both simice and mplab-sim run under microchip technologys mplab integrated development environment (ide) software. specifically, simice provides hardware sim- ulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrollers. simice works in conjunction with mplab-sim to pro- vide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valu- able debugging tool for entry-level system develop- ment. 9.13 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 9.14 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 9.15 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals. pic16c505 ds40192c-page 54 ? 1999 microchip technology inc. 9.16 picdem-17 the picdem-17 is an evaluation board that demon- strates the capabilities of several microchip microcon- trollers, including pic17c752, pic17c756, pic17c762, and pic17c766. all necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. a programmed sample is included, and the user may erase it and program it with the other sample programs using the pro mate ii or picstart plus device programmers and easily debug and test the sample code. in addition, picdem-17 sup- ports down-loading of programs to and executing out of external flash memory on board. the picdem-17 is also usable with the mplab-ice or picmaster emu- lator, and all of the sample programs can be run and modified using either emulator. additionally, a gener- ous prototype area is available for user hardware. 9.17 seeval evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system. 9.18 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. ? 1999 microchip technology inc. ds40192c-page 55 pic16c505 table 9-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 compiler mplab ? c18 compiler mpasm/mplink emulators mplab ?-ice ** picmaster/picmaster-ce icepic ? low-cost in-circuit emulator debugger mplab-icd in-circuit debugger * * programmers picstart a plus low-cost universal dev. kit ** pro mate a ii universal programmer ** demo boards and eval kits simice picdem-1 ? picdem-2 ? ? picdem-3 picdem-14a picdem-17 k ee l oq ? evaluation kit k ee l oq transponder kit microid ? programmers kit 125 khz microid developers kit 125 khz anticollision microid developers kit 13.56 mhz anticollision microid developers kit mcp2510 can developers kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab-icd in-circuit deb ugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77 ** contact microchip technology inc. for availability date. ? development tool is available on select devices. pic16c505 ds40192c-page 56 ? 1999 microchip technology inc. notes: 1999 microchip technology inc. ds40192c-page 57 pic16c505 10.0 electrical characteristics - pic16c505 absolute maximum ratings? ambient temperature under bias ................................................................................................. .......... C40c to +125c storage temperature ............................................................................................................ ................. C65c to +150c voltage on v dd with respect to v ss ....................................................................................................................0 to +7 v voltage on mclr with respect to v ss ...............................................................................................................0 to +14 v voltage on all other pins with respect to v ss ............................................................................... C0.6 v to (v dd + 0.6 v) total power dissipation (1) ............................................................................................................................... .....700 mw max. current out of v ss pin ........................................................................................................................... .......150 ma max. current into v dd pin ........................................................................................................................... ..........125 ma input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin........................................................................................ ........................25 ma max. output current sourced by any i/o pin..................................................................................... ......................25 ma max. output current sourced by i/o port ....................................................................................... ......................100 ma max. output current sunk by i/o port .......................................................................................... ........................100 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pic16c505 ds40192c-page 58 1999 microchip technology inc. figure 10-1: pic16c505 voltage-frequency graph, 0 c t a +70 c figure 10-2: pic16c505 voltage-frequency graph, -40 c t a 0 c, +70 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. 1999 microchip technology inc. ds40192c-page 59 pic16c505 figure 10-3: pic16lc505 voltage-frequency graph, -40 c t a +85 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: the maximum rated speed of the part limits the permissible combinations of voltage and frequency. please reference the product identification system section for the maximum rated speed of the parts. pic16c505 ds40192c-page 60 1999 microchip technology inc. 10.1 dc characteristics: pic16c505-04 (commercial, industrial, extended) pic16c505-20(commercial, industrial, extended) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) parm. no. characteristic sym min typ (1) max units conditions d001 supply voltage v dd 3.0 5.5 v see figure 10-1 through figure 10-3 d002 ram data retention voltage (2) v dr 1.5* v device in sleep mode d003 v dd start voltage to ensure power-on reset v por v ss v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset sv dd 0.05* v/ms see section on power-on reset for details d010 supply current (3) i dd 0.8 0.6 3 4 4.5 19 1.4 1.0 7 12 16 27 ma ma ma ma ma m a f osc = 4mhz, v dd = 5.5v, wdt disabled (note 4)* f osc = 4mhz, v dd = 3.0v, wdt disabled (note 4) f osc = 10mhz, v dd = 3.0v, wdt disabled (note 6) f osc = 20mhz, v dd = 4.5v, wdt disabled f osc = 20mhz, v dd = 5.5v, wdt disabled* f osc = 32khz, v dd = 3.0v, wdt disabled (note 6) d020 power-down current (5) i pd 0.25 0.4 3 5 4 5.5 8 14 m a m a m a m a v dd = 3.0v (note 6) v dd = 4.5v* (note 6) v dd = 5.5v, industrial v dd = 5.5v, extended temp. d022 wdt current (5) d i wdt 2.2 5 m av dd = 3.0v (note 6) 1a lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency fosc 0 0 0 0 200 4 4 20 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. note 1: data in the typical (typ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator t ype, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in kohm. 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 6: commercial temperature range only. 1999 microchip technology inc. ds40192c-page 61 pic16c505 10.2 dc characteristics: pic16lc505-04 (commercial, industrial) dc characteristics power supply pins standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) parm. no. characteristic sym min typ (1) max units conditions d001 supply voltage v dd 2.5 5.5 v see figure 10-1 through figure 10-3 d002 ram data retention voltage (2) v dr 1.5* v device in sleep mode d003 v dd start voltage to ensure power-on reset v por v ss v see section on power-on reset for details d004 v dd rise rate to ensure power-on reset sv dd 0.05* v/ms see section on power-on reset for details d010 supply current (3) i dd 0.8 0.4 15 1.4 0.8 23 ma ma m a f osc = 4mhz, v dd = 5.5v, wdt disabled (note 4)* f osc = 4mhz, v dd = 2.5v, wdt disabled (note 4) f osc = 32khz, v dd = 2.5v, wdt disabled (note 6) d020 power-down current (5) i pd 0.25 0.25 3 3 4 8 m a m a m a v dd = 2.5v (note 6) v dd = 3.0v * (note 6) v dd = 5.5v industrial d022 wdt current (5) d i wdt 2.0 4 m av dd = 2.5v (note 6) 1a lp oscillator operating frequency rc oscillator operating frequency xt oscillator operating frequency hs oscillator operating frequency f osc 0 0 0 0 200 4 4 4 khz mhz mhz mhz all temperatures all temperatures all temperatures all temperatures * these parameters are characterized but not tested. note 1: data in the typical (typ) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator t ype, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in kohm. 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 6: commercial temperature range only. pic16c505 ds40192c-page 62 1999 microchip technology inc. 10.3 dc characteristics: pic16c505-04 (commercial, industrial, extended) pic16c505-20(commercial, industrial, extended) pic16lc505-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c t a +70c (commercial) C40c t a +85c (industrial) C40c t a +125c (extended) operating voltage v dd range as described in dc spec section 10.1 and section 10.3. param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss 0.8v v for all 4.5 v dd 5.5v d030a v ss 0.15v dd votherwise d031 with schmitt trigger buffer v ss 0.2v dd v d032 mclr, rc5/t0cki (in extrc mode) v ss 0.2v dd v d033 osc1 (in xt, hs and lp) v ss 0.3v dd vnote1 input high voltage i/o ports v ih d040 with ttl buffer 2.0 v dd v4.5 v dd 5.5v d040a 0.25v dd + 0.8v dd v dd v otherwise d041 with schmitt trigger buffer 0.8v dd v dd v for entire v dd range d042 mclr, rc5/t0cki 0.8v dd v dd v d042a osc1 (xt, hs and lp) 0.7v dd v dd vnote1 d043 osc1 (in extrc mode) 0.9v dd v dd v d070 gpio weak pull-up current (note 4) i pur 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports i il 1 m avss v pin v dd , pin at hi-impedance d061 gp3/mclr i (note 5) 30 m avss v pin v dd d061a gp3/mclr i (note 6) 5 m avss v pin v dd d063 osc1 5 m avss v pin v dd , xt, hs and lp osc configuration output low voltage d080 i/o ports/clkout v ol 0.6 v i ol = 8.5 ma, v dd = 4.5v, C40 c to +85 c d080a 0.6 v i ol = 7.0 ma, v dd = 4.5v, C40 c to +125 c d083 osc2 0.6 v i ol = 1.6 ma, v dd = 4.5v, C40 c to +85 c d083a 0.6 v i ol = 1.2 ma, v dd = 4.5v, C40 c to +125 c ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c505 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent nor- mal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: does not include gp3. for gp3 see parameters d061 and d061a. 5: this spec. applies to gp3/mclr configured as external mclr and gp3/mclr configured as input with internal pull-up enabled. 6: this spec. applies when gp3/mclr is configured as an input with pull-up disabled. the leakage current of the mclr circuit is higher than the standard i/o logic. 1999 microchip technology inc. ds40192c-page 63 pic16c505 output high voltage d090 i/o ports/clkout (note 3) v oh v dd - 0.7 vi oh = -3.0 ma, v dd = 4.5v, C40 c to +85 c d090a v dd - 0.7 vi oh = -2.5 ma, v dd = 4.5v, C40 c to +125 c d092 osc2 v dd - 0.7 vi oh = -1.3 ma, v dd = 4.5v, C40 c to +85 c d092a v dd - 0.7 vi oh = -1.0 ma, v dd = 4.5v, C40 c to +125 c capacitive loading specs on output pins d100 osc2 pin c osc2 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 c io 50 pf dc characteristics standard operating conditions (unless otherwise specified) operating temperature 0c t a +70c (commercial) C40c t a +85c (industrial) C40c t a +125c (extended) operating voltage v dd range as described in dc spec section 10.1 and section 10.3. param no. characteristic sym min typ? max units conditions ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c505 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent nor- mal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: does not include gp3. for gp3 see parameters d061 and d061a. 5: this spec. applies to gp3/mclr configured as external mclr and gp3/mclr configured as input with internal pull-up enabled. 6: this spec. applies when gp3/mclr is configured as an input with pull-up disabled. the leakage current of the mclr circuit is higher than the standard i/o logic. pic16c505 ds40192c-page 64 1999 microchip technology inc. table 10-1: pull-up resistor ranges - pic16c505 v dd (volts) temperature ( c) min typ max units rb0/rb1/rb4 2.5 C40 38k 42k 63k w 25 42k 48k 63k w 85 42k 49k 63k w 125 50k 55k 63k w 5.5 C40 15k 17k 20k w 25 18k 20k 23k w 85 19k 22k 25k w 125 22k 24k 28k w rb3 2.5 C40 285k 346k 417k w 25 343k 414k 532k w 85 368k 457k 532k w 125 431k 504k 593k w 5.5 C40 247k 292k 360k w 25 288k 341k 437k w 85 306k 371k 448k w 125 351k 407k 500k w * these parameters are characterized but not tested. 1999 microchip technology inc. ds40192c-page 65 pic16c505 10.4 timing parameter symbology and load conditions - pic16c505 the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t ffrequency ttime lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance figure 10-4: load conditions - pic16c505 c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 pic16c505 ds40192c-page 66 1999 microchip technology inc. 10.5 timing diagrams and specifications figure 10-5: external clock timing - pic16c505 table 10-2: external clock timing requirements - pic16c505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units conditions 1a f osc external clkin frequency (2) dc 4 mhz xt osc mode dc 4 mhz hs osc mode (pic16c505-04) dc 20 mhz hs osc mode (pic16c505-20) dc 200 khz lp osc mode oscillator frequency (2) dc 4 mhz extrc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode (pic16c505-04) dc 200 khz lp osc mode 1t osc external clkin period (2) 250 ns xt osc mode 50 ns hs osc mode (pic16c505-20) s lp osc mode oscillator period (2) 250 ns extrc osc mode 250 10,000 ns xt osc mode 250 250 ns hs ocs mode (pic16c505-04) 50 250 ns hs ocs mode (pic16c505-20) 5slp osc mode 2t cy instruction cycle time 4/f osc dc ns 200 ns * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. osc1 q4 q1 q2 q3 q4 q1 133 44 2 1999 microchip technology inc. ds40192c-page 67 pic16c505 table 10-3: calibrated internal rc frequencies - pic16c505 3 tosl, tosh clock in (osc1) low or high time 50* ns xt oscillator 2* s lp oscillator 10 ns hs oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25* ns xt oscillator 50* ns lp oscillator 15 ns hs oscillator ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min* typ (1) max* units conditions internal calibrated rc frequency 3.65 4.00 4.28 mhz v dd = 5.0v internal calibrated rc frequency 3.55 4.00 4.31 mhz v dd = 2.5v * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. table 10-2: external clock timing requirements - pic16c505 (continued) ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial), C40 c t a +85 c (industrial), C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. pic16c505 ds40192c-page 68 1999 microchip technology inc. figure 10-6: i/o timing - pic16c505 table 10-4: timing requirements - pic16c505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units 17 tosh2iov osc1 - (q1 cycle) to port out valid (2,3) 100* ns 18 tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) (2) tbd ns 19 tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20 tior port output rise time (3) 10 25** ns 21 tiof port output fall time (3) 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. note 1: data in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 10-4 for loading conditions. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19 1999 microchip technology inc. ds40192c-page 69 pic16c505 figure 10-7: reset, watchdog timer, and device reset timer timing - pic16c505 table 10-5: reset, watchdog timer, and device reset timer - pic16c505 table 10-6: drt (device reset timer period - pic16c505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 2000* ns v dd = 5.0 v 31 twdt watchdog timer time-out period (no prescaler) 9* 18* 30* ms v dd = 5.0 v (commercial) 32 t drt device reset timer period(2) 9* 18* 30* ms v dd = 5.0 v (commercial) 34 tio z i/o hi-impedance from mclr low 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. oscillator configuration por reset subsequent resets intrc & extrc 18 ms (typical) 300 s (typical) xt, hs & lp 18 ms (typical) 18 ms (typical) v dd mclr internal por drt timeout internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) 30 (note 2) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: runs in mclr or wdt reset only in xt, lp and hs modes. pic16c505 ds40192c-page 70 1999 microchip technology inc. figure 10-8: timer0 clock timings - pic16c505 table 10-7: timer0 clock requirements - pic16c505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature 0 c t a +70 c (commercial) C40 c t a +85 c (industrial) C40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1. parm no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ns with prescaler 10* ns 42 tt0p t0cki period 20 or t cy + 40* n ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (typ) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42 1999 microchip technology inc. ds40192c-page 71 pic16c505 11.0 dc and ac characteristics - pic16c505 the graphs and tables provided in this section are for design guidance and are not tested. in some graphs or tables the data presented are outside specified operating range (e.g., outside specified v dd range). this is for information only and devices will operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean C 3 s ) respectively, where s is standard deviation. figure 11-1: calibrated internal rc frequency range vs. temperature (v dd = 5.0v) (internal rc is calibrated to 25c, 5.0v) figure 11-2: calibrated internal rc frequency range vs. temperature (v dd = 2.5v) (internal rc is calibrated to 25c, 5.0v) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 0 max. mi n. frequency (mhz) temperature (deg.c) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 0 max. mi n . frequency (mhz) temperature (deg.c) pic16c505 ds40192c-page 72 1999 microchip technology inc. table 11-1: dynamic i dd (typical) - wdt enabled, 25c figure 11-3: wdt timer time-out period vs. v dd figure 11-4: short drt period vs. v dd oscillator frequency v dd = 3.0v (1) v dd = 5.5v external rc 4 mhz 240 a (2) 800 a (2) internal rc 4 mhz 320 a 800 a xt 4 mhz 300 a 800 a lp 32 khz 19 a 50 a hs 20 mhz n/a 4.5 ma note 1: lp oscillator based on v dd = 2.5v 2: does not include current through external r&c. min C40 c ty p + 2 5 c max +85 c max +125 c 55 50 45 40 35 30 25 20 15 10 0 2.5 3.5 4.5 5.5 6.5 v dd (volts) wdt period ( s) min C40 c ty p + 2 5 c max +85 c max +125 c 950 850 750 650 550 450 350 250 150 0 0 2.5 3.5 4.5 5.5 6.5 v dd (volts) wdt period ( s) 1999 microchip technology inc. ds40192c-page 73 pic16c505 figure 11-5: i oh vs. v oh , v dd = 2.5 v figure 11-6: i oh vs. v oh , v dd = 5.5 v 500m 1.0 1.5 v oh (volts) i oh (ma) 2.0 2.5 0 -1 -2 -3 -4 -5 -6 -7 m i n + 1 2 5 c m a x C 4 0 c t y p + 2 5 c m i n + 8 5 c 3.5 4.0 4.5 v oh (volts) i oh (ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 m i n + 1 2 5 c m a x C 4 0 c t y p + 2 5 c m i n + 8 5 c figure 11-7: i ol vs. v ol , v dd = 2.5 v figure 11-8: i ol vs. v ol , v dd = 5.5 v 25 20 15 10 5 0 250.0m 500.0m 1.0 v ol (volts) i ol (ma) min +85 c max C40 c ty p + 2 5 c 0 min +125 c 50 40 30 20 10 0 500.0m 750.0m 1.0 v ol (volts) i ol (ma) 250.0m min +85 c max C40 c ty p + 2 5 c min +125 c pic16c505 ds40192c-page 74 1999 microchip technology inc. notes: 1999 microchip technology inc. ds40192c-page 75 pic16c505 11.0 packaging information 11.1 package marking information xxxxxxxxxxxxxx xxxxxxxxxxxxxx aabbcde 14-lead pdip (300 mil) example 14-lead soic (150 mil) xxxxxxxxxx aabbcde 14-lead windowed ceramic (300 mil) xxxxxx xxx example example 16c505-04i/p built 4 speed 9904saz 16c505-04i 9904saz 16c505 jw legend: mm...m microchip part number information xx...x customer specific information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week 01) c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. pic16c505 ds40192c-page 76 1999 microchip technology inc. 14-lead plastic dual in-line (p) C 300 mil (pdip) e1 n d 1 2 eb b e c a a1 b b1 l a2 p a units inches* millimeters dimension limits min nom max min nom max number of pins n 14 14 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .740 .750 .760 18.80 19.05 19.30 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top a 51015 51015 b 51015 51015 mold draft angle bottom *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-005 1999 microchip technology inc. ds40192c-page 77 pic16c505 14-lead plastic small outline (sl) C narrow, 150 mil (soic) foot angle f 048048 15 12 0 15 12 0 b mold draft angle bottom 15 12 0 15 12 0 a mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 8.81 8.69 8.56 .347 .342 .337 d overall length 3.99 3.90 3.81 .157 .154 .150 e1 molded package width 6.20 5.99 5.79 .244 .236 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 h l c b 45 f a a2 a a1 *controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-065 pic16c505 ds40192c-page 78 1999 microchip technology inc. 14-lead ceramic side brazed dual in-line with window (jw) C 300 mil 7.11 6.86 6.60 .280 .270 .260 u lid width 11.68 11.43 11.18 .460 .450 .440 t lid length 4.34 4.22 4.09 .171 .166 .161 w window diameter 8.23 7.87 7.52 .324 .310 .296 eb overall row spacing 0.51 0.46 0.41 .020 .018 .016 b lower lead width 1.42 1.37 1.32 .056 .054 .052 b1 upper lead width 0.30 0.25 0.20 .012 .010 .008 c lead thickness 3.81 3.56 3.30 .150 .140 .130 l tip to seating plane 17.96 17.78 17.60 .707 .700 .693 d overall length 7.62 7.37 7.11 .300 .290 .280 e1 package width 1.14 0.89 0.64 .045 .035 .025 a1 standoff 3.56 3.05 2.54 .140 .120 .100 a2 top of body to seating plane 4.62 4.11 3.61 .182 .162 .142 a top to seating plane 2.54 .100 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters inches* units t w u c eb 2 1 d n e1 p a2 l a1 a b1 b *controlling parameter jedec equivalent: ms-015 drawing no. c04-107 1999 microchip technology inc. ds40192b-page 79 pic16c505 index a alu ....................................................................................... 7 applications........................................................................... 3 architectural overview .......................................................... 7 assembler mpasm assembler..................................................... 51 b block diagram on-chip reset circuit ................................................. 33 timer0......................................................................... 23 tmr0/wdt prescaler................................................. 26 watchdog timer.......................................................... 35 brown-out protection circuit .............................................. 36 c cal0 bit .............................................................................. 16 cal1 bit .............................................................................. 16 cal2 bit .............................................................................. 16 cal3 bit .............................................................................. 16 calfst bit ......................................................................... 16 calslw bit ........................................................................ 16 carry ..................................................................................... 7 clocking scheme ................................................................ 10 code protection ............................................................ 27, 37 configuration bits................................................................ 27 configuration word ............................................................. 27 d dc and ac characteristics ................................................. 71 development support ......................................................... 51 device varieties .................................................................... 5 digit carry ............................................................................. 7 e errata .................................................................................... 2 f family of devices pic16c505 ................................................................... 4 fsr ..................................................................................... 18 i i/o interfacing ..................................................................... 19 i/o ports .............................................................................. 19 i/o programming considerations........................................ 20 id locations .................................................................. 27, 37 indf.................................................................................... 18 indirect data addressing..................................................... 18 instruction cycle ................................................................. 10 instruction flow/pipelining .................................................. 10 instruction set summary..................................................... 40 k keeloq evaluation and programming tools.................... 54 l loading of pc ..................................................................... 17 m memory organization.......................................................... 11 data memory .............................................................. 12 program memory ........................................................ 11 mplab integrated development environment software .... 51 o option register................................................................ 15 osc selection ..................................................................... 27 osccal register............................................................... 16 oscillator configurations ..................................................... 28 oscillator types hs............................................................................... 28 lp ............................................................................... 28 rc .............................................................................. 28 xt ............................................................................... 28 p package marking information ............................................. 75 packaging information ........................................................ 75 picdem-1 low-cost picmicro demo board ..................... 53 picdem-2 low-cost pic16cxx demo board................... 53 picdem-3 low-cost pic16cxxx demo board ................ 53 picstart plus entry level development system ......... 53 por device reset timer (drt) ................................... 27, 34 pd ............................................................................... 36 power-on reset (por).............................................. 27 to ............................................................................... 36 portb ............................................................................... 19 power-down mode ............................................................. 37 prescaler ............................................................................ 26 pro mate ii universal programmer .............................. 53 program counter ................................................................ 17 q q cycles .............................................................................. 10 r rc oscillator....................................................................... 29 read modify write .............................................................. 20 register file map................................................................ 12 registers special function ......................................................... 13 reset .................................................................................. 27 reset on brown-out ........................................................... 36 s seeval evaluation and programming system .............. 54 sleep .......................................................................... 27, 37 software simulator (mplab-sim) ...................................... 52 special features of the cpu .............................................. 27 special function registers ................................................. 13 stack................................................................................... 17 status ............................................................................... 7 status register ............................................................... 14 t timer0 switching prescaler assignment ................................ 26 timer0 ........................................................................ 23 timer0 (tmr0) module .............................................. 23 tmr0 with external clock .......................................... 25 timing diagrams and specifications .................................. 66 timing parameter symbology and load conditions .......... 65 tris registers ................................................................... 19 w wake-up from sleep......................................................... 37 watchdog timer (wdt)................................................ 27, 34 period ......................................................................... 35 programming considerations ..................................... 35 www, on-line support ....................................................... 2 z zero bit ................................................................................. 7 pic16c505 ds40192b-page 80 1999 microchip technology inc. notes: 1999 microchip technology inc. ds40192c-page 81 pic16c505 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events 981103 pic16c505 ds40192c-page 82 1999 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40192c pic16c505 1999 microchip technology inc. ds40192c-page 83 pic16c505 pic16c505 product identification system please contact your local sales office for exact ordering procedures. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. pattern: special requirements package: sl = 150 mil soic p = 300 mil pdip jw = 300 mil windowed ceramic side brazed temperature range: -=0 c to +70 c i=-40 c to +85 c e=-40 c to +125 c frequency range: 04 = 4 mhz (xt, intrc, extrc osc) 20 = 20 mhz (hs osc) device pic16c505 pic16lc505 pic16c505t (tape & reel for soic only) pic16lc505t (tape & reel for soic only) part no. -xx x /xx xxx examples a) pic16c505-04/p commercial temp., pdip package, 4 mhz, normal v dd limits b) pic16c505-04i/sl industrial temp., soic package, 4 mhz, normal v dd limits c) pic16c505-04i/p industrial temp., pdip package, 4 mhz, normal v dd limits ? 2002 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. note the following details of the code protection feature on picmicro ? mcus. the picmicro family meets the specifications contained in the microchip data sheet. microchip believes that its family of picmicro microcontrollers is one of the most secure products of its kind on the market to day, when used in the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowl - edge, require using the picmicro microcontroller in a manner outside the operating specifications contained in the data sheet. the person doing so may be engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ? unbreakable ? . code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our product. if you have any further questions about this matter, please contact the local sales office nearest to you. ? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-6766200 fax: 86-28-6766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 hong kong microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 01/18/02 w orldwide s ales and s ervice |
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